1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT); and particularly to a method for manufacturing a TFT typically used in a liquid crystal display (LCD).
2. Related Art
Generally, a conventional bottom gate type TFT used in an LCD includes a substrate, a gate electrode formed on the substrate, a gate insulation layer formed on the gate electrode, an amorphous silicon (a-Si) layer formed on the gate insulation layer, two impurity-doped a-Si layers formed on two ends of the a-Si layer respectively, a source electrode formed on one of the impurity-doped a-Si layers and the gate insulation layer, and a drain electrode formed on the other impurity-doped a-Si layer and the gate insulation layer.
Referring to FIG. 4, a conventional method of manufacturing a bottom gate type TFT includes the steps of:                step 10 (as shown in FIG. 5): an insulating substrate 31 having a gate metal layer 32 and a first photo-resist layer 33 formed thereon is provided.        step 11 (as shown in FIG. 6): a gate electrode 42 is formed mainly by patterning the gate metal layer 32 using a first photolithographic process, which includes exposing and developing the first photo-resist layer 33 and etching the gate metal layer 32.        step 12 (as shown in FIG. 7): a gate insulation layer 51, an a-Si layer 52, an impurity-doped a-Si layer 53, a metal layer 54 (for the source and the drain electrodes) and a second photo-resist layer 55 are coated on the gate electrode 42 and the insulating substrate 31, in that order from bottom to top.        step 13 (as shown in FIG. 8): a photomask having three light shielding regions 61, 62, 63 and two slits between the light shielding regions 61, 62, 63 is provided.        step 14 (as shown in FIG. 9): a source and drain pattern is formed; in particular, the second photo-resist layer 55 is exposed and developed, and then a residual portion of the second photo-resist layer 55 is wiped off to form a photo-resist structure 65 and a recess 66; then the metal layer 54 is wet etched, wherein a portion of the metal layer 54 which is not covered by the photo-resist structure 65 is wiped off, thereby forming a source/drain electrode pattern 74, as shown in FIG. 10.        step 15 (as shown in FIG. 11): a channel layer 82 and an impurity-doped a-Si pattern 83 are formed; in particular, the a-Si layer 52 and the impurity-doped a-Si layer 53 are dry etched, wherein portions of the a-Si layer 52 and the impurity-doped a-Si layer 53 which are not covered by the source/drain electrode pattern 74 are wiped off, thereby forming the channel layer 82 and the impurity-doped a-Si pattern 83. Further, in the above-described dry etching, the photo-resist structure 65 is constantly corroded, thereby forming a through hole 66a in a center of the photo-resist structure 65, as shown in FIG. 12.        step 16 (as shown in FIG. 13): the source electrode 84, the drain electrode 85, the source ohmic contact layer 832 and the drain ohmic contact layer 831 are formed; in particular, the source/drain electrode pattern 74 and the impurity-doped a-Si pattern 83 are etched, wherein portions of the source/drain electrode pattern 74 and the impurity-doped a-Si pattern 83 corresponding to the through hole 66a are wiped off. Consequently, a contact hole 86, the source and drain electrodes 84, 85, and the source and drain ohmic contact layers 832, 831 are formed.        step 17: a passivation layer is coated on top of the hitherto-formed structure.        step 18: a passivation pattern is obtained using a third photolithographic process, which includes exposing and developing a third photo-resist layer and etching the passivation layer.        step 19: an electrically conductive layer is coated on the hitherto-formed structure.        step 20: a pixel electrode is formed.        
Referring to FIG. 14, a pixel unit of a conventional LCD is shown. The pixel unit has a thin film transistor. The thin film transistor has a source electrode 91 having a generally U-shaped structure, and a drain electrode 92. The drain electrode 92 and the source electrode 91 define a generally U-shaped gap 93 therebetween.
FIG. 15 is a schematic, top plan view of a channel portion of a second photomask 120 used in manufacturing an array of bottom gate type TFTs according to the above-described method. The photomask 120 has a first photomask pattern 91A corresponding to the source electrode 91, a second photomask pattern 92A corresponding to the drain electrode 92, and a third photomask pattern 93A corresponding to the U-shaped gap 93. The third photomask pattern 93A includes two slits each having a generally U-shaped configuration. Light beams transmit through the two slits and illuminate the second photo-resist layer 55 and thereby form the photo-resist structure 65 having the recess 66. The photo-resist structure 65 has a thin layer portion corresponding to the recess 66. However, a width WD of bending portions D of the third photomask pattern 93A generally is wider than a width W0of other portions of the third photornask pattern 93A (except for certain end portions E). This means transmittance of light at the bending portions D is increased, and the second photo-resist layer 55 at these portions is liable to be over-exposed. If this happens, the bottom gate type TFT may be improperly formed and unworkable or unsatisfactory. That is, the yield rate of the array of bottom gate type TFTs formed in mass production may be unduly low.
It is desired to provide a method for manufacturing a TFT which overcomes the above-described problems.